6. System Interface Operations
The cluster coordinator arbitrates the multiprocessors using the SysReq*, SysGnt*, and SysRel* signals.
A processor request issued by an R10000 processor in master state is observed as an external request by any R10000 processors in the slave state on the cluster bus. This is described Table 6-31.
Table 6-31 Relationship Between Processor and External Requests for the Cluster Bus 
In the same manner, a processor coherency data response issued by a processor in the master state is observed as an external block data response by any processors in the slave state.
External coherency requests that target a processor are handled in FIFO order and result in processor coherency state responses. If an external coherency request that targets a processor hits a DirtyExclusive secondary cache block, the processor also provides a processor coherency data response.
Figure 6-27 presents an example of a processor read request with four R10000 processors residing on the cluster bus. The CohPrcReqTar mode bit is asserted for a snoopy-based coherency protocol. R100000 issues a processor coherent read exclusive request. This is observed as an external intervention exclusive request by R100001, R100002, and R100003. R100001 and R100003 respond with Invalid processor coherency state responses. R100002 responds with a DirtyExclusive processor coherency state response. Based on these processor coherency state responses, the cluster coordinator allows R100002 to become master of the System interface so that it may provide a processor coherency data response, which will be observed as an external block data response by R100000. Finally, the cluster coordinator issues an external ACK completion response to forward the external block data response and to free the request number.
Figure 6-27 R10000 Multiprocessor Cluster Processor Read Request Example
Figure 6-28 presents an example of a processor upgrade request with four R10000 processors residing on the cluster bus. The CohPrcReqTar mode bit is asserted for a snoopy-based coherency protocol. R100000 issues a processor upgrade request, observed as an external invalidate request by R100001, R100002, and R100003. R100002 and R100003 provide Shared processor coherency state responses. R100001 provides an Invalid processor coherency state response. Based on these processor coherency state responses, the cluster coordinator issues an external ACK completion response for the processor upgrade request to indicate that the request was successful and to free the request number.
Figure 6-28 R10000 Multiprocessor Cluster Processor Upgrade Request Example
